@User xschem is very small and has a low footprint. However normally you will not use a schematic for a SoC or a Microprocessor, because these things are designed with a 'verilog (or more in general a RTL description) to layout' flow, where logic synthesis tools, static timing analyzers, memory generators, standard cell placement and routing tools (and many other tools in the chain) allow you to produce a complete layout. Schematic editors are more used for analog design, for creating analog blocks (RF, voltage regulators, charge pumps, PLLs, ADC/DACs etc) for block prototyping, new ideas exploration, or for creating a high level description of blocks interconnected together, each one in turn described with some RTL or transistor level implementation. Anyway, i have imported a synthetyzed module from spice netlist, (Thank you @User) containing 50K gates and 200K elements (including wires, net labels etc) (such blocks are normally not imported in a schematic). Xschem required 160MB virtual memory and 130MB resident set to load and handle the circuit. My system is a simple laptop with 4GB ram, but i am not supposed to run a full RTL2LAYOUT flow on this. This imported block was used to do a clock tree inspection, to verify fanout and buffering, however there are tools that do this task automatically, so this import was more a stress test for xschem :-)