@User: There are several ways. You can synthesize with openlane or qflow, finish through routing, then extract a SPICE netlist from magic. Or you can use qflow to get an xspice output, which simulates a lot faster in ngspice (however, I think the xspice output from sky130 in qflow is broken and was thinking of taking a look at it today).

Oh okay, thanks @Tim Edwards

@Surag P as Tim explained, in this case there is no need to go thru a schematic. Once you have a spice (or Xspice) netlist from the synthetized verilog design you can simulate it, assuming it is not too big.