Weston Braun
05/29/2021, 9:42 PMTim Edwards
05/29/2021, 11:58 PMStefan Schippers
05/31/2021, 5:45 AM.subckt eye_diagram node1 node2 ...
.connect node1 node2
...
.ends
Handling subcircuit 'pass-thru' nodes in the schematic is not trivial since a choice has to be made about the node to keep and the node to drop.
In addition, since xschem outputs also Verilog and VHDL netlists, any 'node merging' needs to be checked also with these 2 formats.
In many situations i have used the '0V voltage source connection' to simulate a buffer, later replaced with an actual buffer in the subcircuit. In this case the 0v or 0Ω connection is perfect, since the output node is retained in the waveform viewer.Weston Braun
05/31/2021, 6:37 AMWeston Braun
05/31/2021, 6:38 AMWeston Braun
05/31/2021, 6:38 AMTim Edwards
05/31/2021, 2:48 PM