Hi, @User, open the

test_analog.sch

as a top level, do not descend into it from a parent schematic (menu

File->Open->xschem_sky130->sky130_tests->test_analog.sch

) This should fix the problem. If not the most likely cause is the voltages are not saved into the raw file, but i tested the example right now and it seems ok.

Yes it is working correctly now. Thanks👍

Good! The reason is that if you open the parent schematic it is assumed that the simulation is run at the parent schematic level, so node

OUT2

in

test_analog.sch

becomes

x21.OUT2

, since test_analog is now a subcircuit of the parent

top.sch

. This confuses the backannotation code.

Okay!got it 👍