@User I see in the spice netlist (

sky130_fd_sc_hd.spice

) the

inv_1

is declared as:

.subckt sky130_fd_sc_hd__clkinv_1 A VGND VNB VPB VPWR Y

so port order is

input, nsupply, nbody, pbody, psupply, output.

In the above (2nd) picture it looks like the port order is

Input, nsupply, psupply, output, nbody, pbody

. I am sure the port order of extracted subcircuits matches the port order of subcircuit calls in the extracted netlist. However the order is different from the .spice file of the stdcells. I am not sure if this has any impact on LVS, probably not. Just curious.

All of the views in the PDK are made consistent with respect to port order. However, the 2nd netlist above probably came from reading GDS into magic and then extracting a netlist. GDS does not have any way to specify a port order on pins, and so they get randomized (probably scanned left to right or something like that, based on the mask geometry). Netgen will handle that and keep track of the pin ordering on both sides, as long as the pins connect to the same devices internal to the subcircuit.

Thank you for clarifying!

Yes thank you for explaining Tim! For now, I will fix the problem by editing the extracted spice netlist to add prefixes to the subcircuit definitions. A simple

sed

script should do the trick.