@User @User i have added a

reram.sym

symbol in the xschem_sky130 repository. I used the information available in the google github page. (there is a 1t1r example spice netlist i lurked into to see the syntax). However i have not tested this symbol yet, since it probably requires to build a verilogA model and Xyce. I have Xyce, so in one of the next days i will take a deep breath and try this out, being prepared for some initial frustration 🙂

I'd be happy to help, as I recently upgraded my computer and now I have been able to compile Xyce properly and get it to run. I need to go back and look at what branch I should have been using, because I thought that Eric said that he did something to make the ".option scale" work in Xyce as-is. But that may have required a development branch or some setting that I failed to use. But I was able to change the ".option scale" line in

all.spice

to ".options parser scale", and Xyce ran. But compiling verilog-A will be new for me, too.

@User @User is xyce only needed if we are designing in verilog? I do see a spice file in the reram pdk and I was hoping to be able to simulate with just spice netlists and not go verilog-AMS on this

@User: To avoid verilog-AMS it would be necessary to create some kind of non-linear model for the ReRAM, which is certainly doable, but also take a lot of work to get right. Ultimately, you should be able to work from the documentation to check that you have a circuit that applies the right voltage polarity, amplitude, and pulse width to the device for setup/program/deprogram, and for read-back, just simulate with the device as a resistor and make sure that the circuit operates over the range of resistances shown for the high and low resistance states in the measured results.