I throw in a small challenge, just for fun. Suppose i need a 'double clock flip-flop'. This is a device with 2 data pins,

D1

and

D2

, and 2 clocks,

CK1

and

CK2

. It has 1 output pin

Q

that is updated with

D1

on

CK1 rising edge

or

D2

on

CK2 rising edge

. There is a minimum guaranteed distance between the 2 clock rising edge events, or the result will be undefined. The device is Edge triggered, so responds only on rising edges of either CK1 or CK2. What is the simplest working configuration you can get with skywater (

sky130_fd_sc_hd

) standard cells? I prefer implementations with no 'pulse generators'. A simple solution is to create a pulse on clock rising edges (using delay inverter chains) and using latches. However i don't like these solutions as these present huge issues if the device is inserted in a synthetized clocked network, or more of such devices are chained, and are also difficult to handle with STA tools. Double flip-flop truth table:

D1     CK1      D2     CK2      |  Q
-------------------------------------
D1    rising    X   not rising  |  D1
X   not rising  D2    rising    |  D2

'X' means 'Any value'

Consider also adding a

RESET

or

RESET#

input (not shown in truth table) that sets

Q=0

. I have a working implementation but it is not very simple and i am wondering if it can be made simpler. I will show it later, as i don't want to bias your ideas. Hard-core designers could also pick a transistor level schematic of a traditional flip-flop and add a second data pin and second clock input and create a new standard cell, instead of creating this device using existing standard cells.

There is a similar case that I use which has one synchronous input and on asynchronous input. It might be relevant here, depending on your intended application, although the implementation isn't exactly the same. But the implementation is to use a set-reset flop with logic on the !S and !R inputs. The implementation is shown below. You can think of the "reset" as your second clock and "async_data" as your second input. It is not exactly like your implementation becase the device is a flop with respect to "CLK" but a latch with respect to "reset". I like to use this circuit often because it allows me to apply the reset condition for a circuit from an external source. I used it on caravel so that I could have the same base circuit

gpio_control_block

to drive each of the GPIOs, but the power-on state could be set for each one independently with a simple ROM block.

If anyone wants to design a gate-level spice netlist for a new standard cell, I can automatically generate the layout for that new standard cell with my toolchain.

@User this was the simplest true edge triggered double clock flip flop i was ever able to implement, and despite working fine it looks to me a bit over engineered. But any my attempt to make it simpler did not succeed.

@User: Possibly you could get something simpler by using a latch for the first stage of each flop, combining the signals between the first and second stage, and following that with a single latch (whose enable input is some function of CK1 and CK2). The 2nd stage could be a reset latch. I haven't really thought it out in detail; it might not be any simpler than what you came up with.