@User This is definitely an option. In xschem this is already the case for Spice/Verilog/Vhdl netlisting rules. Depending on the selected output netlist format the corresponding rule is used. This could be used to differentiate between ngspice/Xyce/... as well. However the above discussion is not about generating something into the netlist, but visually displaying some information (heavily linked to the simulator output files) in the schematic.

Ah, yes, I didn't read it carefully. That makes it much more complicated.