I'm trying to run post-layout simulation on single...
# xschem
l
I'm trying to run post-layout simulation on single, multi-finger MOSFET I laid out to get a grip on the parasitics of the accesses. I managed to get it running smoothly up until the LVS, however I'm struggling to get the PEX .spice netlist working properly into xschem. The extracted view has no DC connections and I don't know what to do to fix it. To try to include the parasitics I created a .sch file containing the ports and a code instance where I copied the extracted netlist (from Magic). Then I created a symbol for this schematic and tried to run a simple DC sweep to measure the drain current. I got 0 A. Here's the extracted netlist: * SPICE3 file created from nmos_RF_contacts.ext - technology: sky130A .subckt nmos_RF_contacts gate drain source substrate X0 source gate drain substrate sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u X1 drain gate source substrate sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u X2 drain gate source substrate sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u X3 drain gate source substrate sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u X4 source gate drain substrate sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u X5 source gate drain substrate sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u X6 drain gate source substrate sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u X7 drain gate source substrate sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u X8 source gate drain substrate sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u X9 source gate drain substrate sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u C0 gate source 2.57fF C1 drain source 7.90fF C2 gate drain 2.08fF C3 drain substrate 0.39fF C4 source substrate 0.48fF C5 gate substrate 1.30fF .ends And here is a screenshot of the .sch for the extracted mosfet: Any help would be much appreciated :)
j
There's a few ways to do the pex sim, but the shortest path with what you have shown on that image is probably to comment out the first line (subckt) and last line (ends), since it sounds like you are using a symbol of this schematic in your sim. You can also delete the wires on the pins out to the left, but I'm not sure that those would give an error either way. If you posted what your test bench schematic (the DC sweep) looks like someone might be able to help more, as there could be errors there.
l
I will as soon as I get back to my laptop :) What are the other ways, by the way? I'm quite lost
Thanks a lot, @User! I was able to finally get everything working! Now, time to start designing ;)