@User there are 3 ways to do that. 1. use regular pins (ipin.sym, iopin.sym, opin.sym, whatever you feel appropriate) for power nets as well as signal nets. 2. use the 'inherited connection' method. The power nets are declared in the symbol attributes and in the corresponding schematic and will be netlisted as regular subcircuit i/o pins, without having them in the symbol. The net->power connection at the parent schematic level can be set via attributes. The process is explained in this video. 3. Use vdd.sym and/or gnd.sym for vdd /gnd tiers. These symbols will add a .global line in the spice netlist, so these supply nodes will be declared as global and accessible within any subcircuit without having these nodes as symbol interfaces.

Thanks!