<@U02NNT94BK8> the nvt suffix indicates a negative...
# xschems
Stefan Schippers
04/23/2022, 11:09 AM@User the nvt suffix indicates a negative native threshold, so the 03v3_nvt is a (slightly) depletion nmos. If you sweep the vgs from -1V you see the transistor turn on.
r
Ryan R
04/23/2022, 11:13 AMThanks @User - I didnt know the nvt stands for negative threshold. I see no enchancement type 3v3 nmos in the library - is this expected ?
s
Stefan Schippers
04/23/2022, 11:16 AMGood question. I didn't find either, nvt means 'native vt' so there are no special implant masks on this transistor to correct it's threshold.
r
Ryan R
04/23/2022, 11:16 AMOK!
s
Stefan Schippers
04/23/2022, 11:25 AMI think you should use the nfet_g5v0d10v5 transistor. It has the same gate oxide of the 03v3_nvt (and the 05v0_nvt) with different minimum geometrical dimensions.
r
Ryan R
04/23/2022, 2:24 PMLet me check. Basically the reuqirement was to create a voltage divider from 3v3. But supplying the -ve vooltage for nfet on chip is not really desirable
Ryan R
05/04/2022, 10:07 AM@User I instantiated a cell from xschem and dumped spice which output the following , but spice is erroring put saying :
Error on line 0 :
m.xm1.msky130_fd_pr__nfet_g5v0d10v5 net1 net2 0 0 xm1:sky130_fd_pr__nfet_g5v0d10v5__model l= 1.500000000000000e-01 w= 1.000000000000000e+00 nf= 1.000000000000000e+00 ad= 2.900000000000000e-01 as= 2.900000000000000e-01 pd= 2.580000000000000e+00 ps= 2.580000000000000e+00 nrd= 2.900000000000000e-01 nrs= 2.900000000000000e-01 sa= 0.000000000000000e+00 sb= 0.000000000000000e+00 sd= 0.000000000000000e+00 m= 1.000000000000000e+00
could not find a valid modelname
Simulation interrupted due to error!
Spice file :
**.subckt ABC
XM1 net1 net2 GND GND sky130_fd_pr__nfet_g5v0d10v5 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
*XM1 net1 net2 net1 GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
*+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
*+ sa=0 sb=0 sd=0 mult=1 m=1
**.ends
.GLOBAL GND
VGS net2 GND 3.3
VDS net1 GND 3.3
.tran 0.01n 100n
.save all
.lib /sky130_fd_pr_ngspice_ayan/latest/models/sky130.lib.spice tt
.end
-------------------------------------------------
But if i use the commented nmos , its simulating correctly
Ryan R
05/04/2022, 12:32 PM@User Also the spice models for 3v3 nvt doesnt seem to be valid for -ve vgs :
s
Stefan Schippers
05/05/2022, 8:26 AMYes, these devics are not characterized for negative vgs so model behavior is not well defined in these regions.
Stefan Schippers
05/05/2022, 8:28 AM@User for the nfet_g5v0d10v5 the minimum channel length is 0.5 (0.5um), you are using 0.15
r
Ryan R
05/05/2022, 8:44 AMOh. I just used the spice from xschem. Let me modify and recheck
👀 1
Ryan R
05/05/2022, 4:23 PMI removed other params , as below but same error :
I think NVT has also same min transistor length of 0.5
XM1 net1 net2 GND GND sky130_fd_pr__nfet_03v3_nvt L=0.5 W=2
Error on line 0 :
m.xm1.msky130_fd_pr__nfet_03v3_nvt net1 net2 0 0 xm1:sky130_fd_pr__nfet_03v3_nvt__model l= 6.000000000000000e-01 w= 2.000000000000000e+00 nf= 1.000000000000000e+00 ad= 0.000000000000000e+00 as= 0.000000000000000e+00 pd= 0.000000000000000e+00 ps= 0.000000000000000e+00 nrd= 0.000000000000000e+00 nrs= 0.000000000000000e+00 sa= 0.000000000000000e+00 sb= 0.000000000000000e+00 sd= 0.000000000000000e+00
Ryan R
05/06/2022, 10:22 AM@User any idea
s
Stefan Schippers
05/06/2022, 10:37 AMIt appears the only allowed geometries are the following (in your netlist multiply values by 1e6):
+ lmin = 4.95e-07 lmax = 5.05e-07 wmin = 9.995e-06 wmax = 1.0005e-5+ lmin = 4.95e-07 lmax = 5.05e-07 wmin = 9.95e-07 wmax = 1.005e-6+ lmin = 5.95e-07 lmax = 6.05e-07 wmin = 9.95e-07 wmax = 1.005e-6+ lmin = 4.95e-07 lmax = 5.05e-07 wmin = 3.995e-06 wmax = 4.005e-6+ lmin = 4.95e-07 lmax = 5.05e-07 wmin = 4.15e-07 wmax = 4.25e-7+ lmin = 5.95e-07 lmax = 6.05e-07 wmin = 4.15e-07 wmax = 4.25e-7+ lmin = 7.95e-07 lmax = 8.05e-07 wmin = 4.15e-07 wmax = 4.25e-7+ lmin = 4.95e-07 lmax = 5.05e-07 wmin = 6.95e-07 wmax = 7.05e-7+ lmin = 5.95e-07 lmax = 6.05e-07 wmin = 6.95e-07 wmax = 7.05e-7👀 1
Stefan Schippers
05/06/2022, 10:38 AMso first line is for a transistor with L=0.5, W=10, second line for L=0.5, W=1, last line for L=0.6, W=0.7 and so on...
👀 1
7 Views