@User I see magic creates one more subckt level: one subckt for the inverter, one subcircuit for the P and N MOS transistors, finally containing the library transistor subcircuit call. xschem creates the subckt for the inverter with directly the library transistors subcircuit calls. I don't know if the extra hierarchy level creates a mismatch when doing LVS. Also the toplevel subcircuits (xschem and magic) have different port order. I don't know if the order of the i/o pins does matter.

In general , what is the methodology used for LVS in sky130 ? Is it netgen for some native magic/xschem ? The extra hierarchy appearing in magic is due to the instAtiation of some predefined macro cells.

During netgen's LVS, mismatched hierarchies will be flattened until they match or the top level is reached. Port order is irrelevant.

actually from the magic netlists devices are not being recognized. Any ideas

@User: (1) Your top level cell name differs between the schematic and layout (the layout name is

inverter_D1_g5d10_tapped

but the schematic name is

inv_g5D10

. If you want netgen to compare them, then you need to specify the cell name after the file name for each one; i.e.,

lvs "../../xschem/inv_g5D10.spice inv_g5D10" "inverter_D1_g5d10_tapped.spice inverter_D1_g5d10"

. Netgen does not try to derive any subcircuit name from the file name itself. (2) It's possible that you copied the setup file from the PDK to the local directory, but I think you are just missing it from the

lvs

command line, where it should be the argument after the file names (e.g.,

/usr/share/pdk/sky130A/libs.tech/netgen/sky130_setup.tcl

).

@Tim Edwards I updated the cell name in both . (sky130_layouts) 9 % lvs ../../xschem/inv_g5D10.spice inverter_D1_g5d10_tapped.spice /home/ratul619/IIT_study_VM/OpenLane/pdks/open_pdks/sky130/netgen/sky130_setup.tcl Reading setup file /home/ratul619/IIT_study_VM/OpenLane/pdks/open_pdks/sky130/netgen/sky130_setup.tcl Model sky130_fd_pr__nfet_g5v0d10v5 pin 1 == 3 No property as found for device sky130_fd_pr__nfet_g5v0d10v5 No property ad found for device sky130_fd_pr__nfet_g5v0d10v5 No property ps found for device sky130_fd_pr__nfet_g5v0d10v5 No property pd found for device sky130_fd_pr__nfet_g5v0d10v5 No property area found for device sky130_fd_pr__pfet_g5v0d10v5 No property perim found for device sky130_fd_pr__pfet_g5v0d10v5 No property topography found for device sky130_fd_pr__pfet_g5v0d10v5 Comparison output logged to file comp.out Logging to file "comp.out" enabled Circuit ../../xschem/inv_g5D10.spice contains no devices. Result: Verify: no current cell to verify. Logging to file "comp.out" disabled LVS Done. netgen is complaining that the xschem netlist doesnt have any devices> Xschem netlist : ** sch_path: /home/ratul619/IIT_study_VM/xschem/inv_g5D10.sch .subckt inverter_D1_g5d10_tapped IN VSS VDD OUT *.PININFO IN:I VSS:B VDD:B OUT:O XM1 OUT IN VDD VDD sky130_fd_pr__pfet_g5v0d10v5 L=0.6 W=0.840 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' + sa=0 sb=0 sd=0 mult=1 m=1 XM2 OUT IN VSS GND sky130_fd_pr__nfet_g5v0d10v5 L=0.6 W=0.420 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' + sa=0 sb=0 sd=0 mult=1 m=1 .ends .GLOBAL GND .end @Stefan Schippers

Try renaming

../../xschem/inv_g5D10.spice

to

../../xschem/inverter_D1_g5d10_tapped.spice

@Ryan R also if everything fails, try to unselect Xschem's '`Simulation->Use spiceprefix attribute`', so instead of writing out XM1 and XM2 for the mos transistors they will be output as M1 and M2. In sky130 pdk transistor models are implemented via subcircuits, so the extra level of indirection allows to define additional parameters. May be netgen LVS just wants to see the bare devices. This is just a crude guess, i am not expert with netgen LVS.

@Ryan R:

(sky130_layouts) 9 % lvs ../../xschem/inv_g5D10.spice inverter_D1_g5d10_tapped.spice /home/ratul619/IIT_study_VM/OpenLane/pdks/open_pdks/sky130/netgen/sky130_setup.tcl

You did not follow my instruction to put both the file name and the cell name (pair in quotes) for each circuit on the command line.

srry i missed may be this comment. Will reapply