Can anyone clarify me regarding the following information. 1. The submitted design is harnessed with caravel project user project area, which means the user design is a part of caravel SoC which consists the picorv32a processor and other peripherals ( along with the user design ref:https://github.com/efabless/caravel) 2. Is the fabricated chip consists the caravel SoC (along with processor) or only the user design 3. In the example project config file which are parameters should not be changed like DIE area (0 0 900 600). (since the pl target density was mentioned only 0.05 can we change this configuration ref: https://skywater-pdk.slack.com/archives/C017HPHCMEY/p1634150627104800?thread_ts=1634104863.096100&cid=C017HPHCMEY) 4. The user project area was restricted with 38 GPIO but the example counter project consists multiple IO ports more than 38. Are we allowed to use more ports. (ex 20 bit adder need 2 input of 40 ports and 1 output port of 21 bits, as a total 61 IO ports. ref: https://skywater-pdk.slack.com/archives/C017HPHCMEY/p1634355866111300?thread_ts=1634355442.111000&cid=C017HPHCMEY) 5. Are we need to remove the unused input/output/power ports from user_project_wrapper.v or need to leave unconnected with same order. 6. For the digital design Is it enough to copy the design files to verilog directory of caravel or any other files (like gds lef def from openlane project folder) need to be copied to some other caravel directory to run make user_example_project.

1. yes 2. yes, with the SoC unless you make an analog submission which is basically a blank canvas without even padring 3. you are free to change those parameters. I would get rid of absolute die size and let openlane choose the floorplan 4. yes only 38 ios. If you need more you'll have to multiplex them. The padring and caravel lis fixed, we can't add more gpios. 5. don't remove them from user_project_wrapper, but if you don't need all the pins, just don't connect them when you instantiate your design inside it 6. yes you will need verilog as its the source, and the gds and def file are needed to build the user_project_wrapper which is what you submit

is gds and def generated while running make user_example_project or we need to copy from the openlane project directory to caravel directory manually.

it should get copied automatically

I can able to gds files inside caravel_user_project/user_proj_example/runs and also caravel_user_project/gds or def directory. are these gds files same after make.

yes they get copied over

👍

Q: Is the fabricated chip consists the caravel SoC (along with processor) or only the user design A: yes, with the SoC unless you make an analog submission which is basically a blank canvas without even padring If only ... AFAICT the analog submission still has the padring and the RISC-V processor, but some pads in the padring are not attached to it.

no you have 38 ports with 3 signals for each

nice explanation. no i got clear. thank you @Matt Venn and @Christoph Maier