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Hi all, I’m getting this error in the tapeout phase. What is the error exactly and how can I resolve...
# shuttle
m
Hi all, I’m getting this error in the tapeout phase. What is the error exactly and how can I resolve it?
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Job Summary
submitted - 11/10/21 16:27:26 PST
started - 11/10/21 16:55:16 PST
running - 11/10/21 16:55:23 PST
failed - 11/10/21 17:46:04 PST
Logs

[11/10/21 16:27:26 PST] SUBMITTED





[11/10/21 16:55:16 PST] STARTED





[11/10/21 16:55:23 PST] PROJECT GIT INFO
Repository: <https://github.com/manili/vsdmemsoc_mpw3.git> | Branch: HEAD | Commit: 9757fb09d459045a874030d651edeee5750a7f45




[11/10/21 16:55:23 PST] EXTRACTING GDS
Extracting GDS Files




[11/10/21 16:55:24 PST] PROJECT GDS INFO
user_project_wrapper: f683dc66d6824af5ba319c20f2dea1d3bad632aa




[11/10/21 16:55:24 PST] START
Tapeout Started




[11/10/21 16:55:24 PST] STEP UPDATE
Generating Final Layout: Step 1 of 5




[11/10/21 16:56:04 PST] STEP UPDATE
Generating Final Layout: Step 2 of 5




[11/10/21 17:07:43 PST] STEP UPDATE
Generating Final Layout: Step 3 of 5




[11/10/21 17:27:47 PST] STEP UPDATE
Generating Final Layout: Step 4 of 5




[11/10/21 17:38:33 PST] STEP UPDATE
Generating Final Layout: Step 5 of 5




[11/10/21 17:40:16 PST] STEP UPDATE
Converting Final Layout from GDS to OAS




[11/10/21 17:40:53 PST] STEP UPDATE
Executing Check 1 of 2: Klayout Metal Minimum Clear Area Density




[11/10/21 17:45:46 PST] STEP UPDATE
Executing Check 2 of 2: Klayout Field Oxide Mask Density




[11/10/21 17:46:04 PST] FINISH
Executing Finished, the full logs can be found in u6291_mufutau/design/vsdmemsoc/jobs/tapeout/da5c0d78-055d-4fc9-afa7-47362b4afe80/logs




[11/10/21 17:46:04 PST] FAILED
STDOUT: {{Project Git Info}} Repository: <https://github.com/manili/vsdmemsoc_mpw3.git> | Branch: HEAD | Commit: 9757fb09d459045a874030d651edeee5750a7f45
STDOUT: {{Extracting GDS}} Extracting GDS Files
STDOUT: {{Project GDS Info}} user_project_wrapper: f683dc66d6824af5ba319c20f2dea1d3bad632aa
STDOUT: {{START}} Tapeout Started
STDOUT: {{Step Update}} Generating Final Layout: Step 1 of 5
STDOUT: {{Step Update}} Generating Final Layout: Step 2 of 5
STDOUT: {{Step Update}} Generating Final Layout: Step 3 of 5
STDOUT: {{Step Update}} Generating Final Layout: Step 4 of 5
STDOUT: {{Step Update}} Generating Final Layout: Step 5 of 5
STDOUT: {{Step Update}} Converting Final Layout from GDS to OAS
STDOUT: {{Step Update}} Executing Check 1 of 2: Klayout Metal Minimum Clear Area Density
STDERR: [ WARN ] MET Density Check Result: GDS has 1 DRC violations.
STDOUT: {{Step Update}} Executing Check 2 of 2: Klayout Field Oxide Mask Density
STDERR: [ WARN ] FOM Density Check Result: GDS has 0 DRC violations.
STDOUT: {{FINISH}} Executing Finished, the full logs can be found in u6291_mufutau/design/vsdmemsoc/jobs/tapeout/da5c0d78-055d-4fc9-afa7-47362b4afe80/logs
👍 1
a
I had this too, rerunning the entire build seems to have fixed it though
m
@User May I ask, what did you do exactly?
So you rerun the 
tapeout
phase again?
@User @User How can I figure out the issue?
j
@User you have a metal density issue. check your log output for the tapeout job to find out with layer. you are likely under density since precheck catches any over density issues.
if you are under density on metal 4 or 5, it may be an issue with your pdn pitch if you customized it. the pitch may not allow fill_generation to successfully fill between you stripes.
m
Hi @User, Thanks a lot for the reply. I’m using default configs of the config file. This is whatever I did to configure the wrapper (all other options remain the same including pdn’s pitch and spacing size): https://github.com/manili/vsdmemsoc_mpw3/blob/main/openlane/user_project_wrapper/config.tcl
@User Also here’s the configuration of the 
user_proj_example
which is my own digital design: https://github.com/manili/vsdmemsoc_mpw3/blob/main/openlane/user_proj_example/config.tcl
j
which project is yours?
m
@User Both me and Muf are working on this: https://efabless.com/projects/483
@User This is metal density report.
@User Have you ever faced the same issue?
m
not yet...
m
@User Looks like Jeff is pretty much busy. Dunno whom to ask. BTW sorry for the interrupt.
j
@User the issue is your LI density is too high. the requirement is the clear area for LI must be at least 40%. Yours is just short.
h
In the #tapeout-job channel, @User seems to be investigating a similar issue for @User
j
the first thing to check is which decap cells you are using.
taking a look now
m
@User @User That’s great! Thanks a lot for the help. Now what should I do to increase the LI density?
j
yes - you are using the standard decap_12 cell. the recommended cell is sky130_fd_ef_decap_12
let me check on how that gets configured in OpenLane
you are using OpenLane to harden your design?
m
@User Yes I used OpenLane to harden part of my design. And the other part is a custom design (SRAM).
h
I think it's DECAP_CELL
m
@User @User How can I change my DECAP_CELL to sky130_fd_ef_decap_12?
j
set ::env(DECAP_CELL) "sky130_ef_sc_hd__decap_12 sky130_fd_sc_hd__decap_3 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_8"
add the above to your 
config.tcl
for each macro you are hardening with OpenLane
m
@User OK Great! I’ll Give it a try…
Thanks a million @User
BRB with the result
h
@User I guess you meant 
sky130_fd_sc_hd__decap_3
instead of 
sky130_sc_hd__decap_3
j
yes - sorry
m
@User May I ask what would happen if we have under/over density?
I mean during the fabrication process…
m
you wouldn't be allowed to fab, it's like drc
and the reason it's important is that in between processes to build up the layers, often there is a polishing or flattening stage to make sure that everything is flat for the next step
if you only had a few bits of metal 3 in the middle, then they'd stick up on their own
so you fill in the rest of the space with fill patterns, to create a more even layer
I'm not totally sure if I got that right, but it's that kind of reason
✅ 1
m
@User Thanks Matt.
j
thats correct
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