I am trying to run a basic test that is toggling some IOs using the Caravel itself. Here is the link to the gist of the C code and the associated verilog testbench (https://gist.github.com/hadirkhan10/4d210b3703ba93dfd611229f83f6c329) The wave dump shows io pin 3 to be continuously HIGH, and pin 2, pin 4 not being toggled at all. Any ideas what is happening here? This is all Caravel only.

Can't see any thing wrong from the code. I have always ignored the first 8 pins because they are dual use. Maybe you need to do additional config to use them

Interesting. Their dual use is:

// JTAG      = mprj_io[0]           (inout)
    // SDO       = mprj_io[1]           (output)
    // SDI       = mprj_io[2]           (input)
    // CSB       = mprj_io[3]           (input)
    // SCK       = mprj_io[4]           (input)
    // ser_rx    = mprj_io[5]           (input)
    // ser_tx    = mprj_io[6]           (output)
    // irq       = mprj_io[7]           (input)

In File: caravel/verilog/rtl/mgmt_soc.v, I see spi_enable is blocking Bit[2] to [4] assign mgmt_out_data[2] = spi_enabled ? spi_sdo : *mgmt_out_pre[2]*; assign mgmt_out_data[3] = spi_enabled ? spi_csb : *mgmt_out_pre[3]*; assign mgmt_out_data[4] = spi_enabled ? spi_sck : *mgmt_out_pre[4]*;

Oh I see so it keeps the spi_csb HIGH when the hex is loaded in the memory. And the spi_csb maps to pin 3 causing it to stay HIGH for the entire time?

Look like reg_spimaster_config[12] control the SPI enable, Changing reg_spimaster_config = 0xA002; To reg_spimaster_config = 0x8002; Solves the issue