Anyone Pls help to solve this error... Thanks
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Anyone Pls help to solve this error... Thanks
m
@User Maybe post your top gate level verilog.
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This is an analog design
m
@User How are you setting your macro power connections? This might be related https://skywater-pdk.slack.com/archives/C016G7Z8GDR/p1640795235184400?thread_ts=1640693345.183700&cid=C016G7Z8GDR
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