Hi, I am getting this LVS mismatch issue for unmatched pins. I don't know if this is a valid problem as all the pins are there, just the order doesn't match.

It may be that your layout pins are mislabeled. Even though your layout could be topologically equivalent to your verilog netlist, this will cause routing problems at next higher level.

Hmmm, what could be the possible thought process to solve this problem? I haven't seen such problem before while hardening the design..

Just these 6 mismatches, right? Any related error messages in the extraction log? Might be caused by a discrepancy between the top level pin placements in the LEF file and GDS file. You might try checking the coordinates.

Yes just these 6 mismatches. There are multiple messages like these printed in the logs:

Circuit 2 parallel/series network does not match Circuit 1
Circuit 1 instance ANTENNA_616 network:
  M = 1
  M = 1
  M = 1
  M = 1
  M = 1
  M = 1
  M = 1
  M = 1
  M = 1
  M = 1
  M = 1
  M = 1
  M = 1
  M = 1
  M = 1
  M = 1
Resolving automorphisms by pin name.
Netlists match uniquely.
Circuits match correctly.
Result: The top level cell failed pin matching.

Logging to file "/openlane/designs/Ibtida_top_dffram_cv/runs/New_DFFRAM_rtl/results/lvs/Ibtida_top_dffram_cv.lvs.lef.log" disabled
LVS Done.