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We have some verilog macros defined in `openram_defines.v` . This file is included inside the user_p...
# shuttle
h
We have some verilog macros defined in 
openram_defines.v
. This file is included inside the user_project_wrapper. While running 
make verify-io_ports
(just to test if everything is running fine) the simulation errors with “Include file openram_defines.v not found”. Note: this did not happen before the whole MCW simulation changes. Any ideas for the solution? I know iverilog is not able to find it but I am not sure how to make it find it.
m
You can add it to this includes file 
mgmt_core_wrapper/verilog/includes/includes.rtl.caravel_user_project
add 
-v $(USER_PROJECT_VERILOG)/<openram_defines.v path>
h
I tried this, it still did not work
m
can you show me the log?
h
Copy code
export CARAVEL_ROOT=/home/mkhan33/openram_testchip/caravel && make -f /home/mkhan33/openram_testchip/caravel/Makefile check-env
make[1]: Entering directory '/home/mkhan33/openram_testchip'
make[1]: Nothing to be done for 'check-env'.
make[1]: Leaving directory '/home/mkhan33/openram_testchip'
docker run -v /home/mkhan33/openram_testchip:/home/mkhan33/openram_testchip -v /home/mkhan33/shuttle-pdks/new-pdks:/home/mkhan33/shuttle-pdks/new-pdks \
	-v /home/mkhan33/openram_testchip/caravel:/home/mkhan33/openram_testchip/caravel \
	-e TARGET_PATH=/home/mkhan33/openram_testchip -e PDK_ROOT=/home/mkhan33/shuttle-pdks/new-pdks \
	-e CARAVEL_ROOT=/home/mkhan33/openram_testchip/caravel \
	-e TOOLS=/opt/riscv32i \
	-e DESIGNS=/home/mkhan33/openram_testchip \
	-e CORE_VERILOG_PATH=/home/mkhan33/openram_testchip/mgmt_core_wrapper/verilog \
	-e GCC_PREFIX=riscv32-unknown-elf \
	-e MCW_ROOT=/home/mkhan33/openram_testchip/mgmt_core_wrapper \
	-u $(id -u $USER):$(id -g $USER) efabless/dv_setup:latest \
	sh -c "cd /home/mkhan33/openram_testchip/verilog/dv/io_ports && export SIM=RTL && make"
iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
-f/home/mkhan33/openram_testchip/mgmt_core_wrapper/verilog/includes/includes.rtl.caravel_user_project -o io_ports.vvp io_ports_tb.v
/home/mkhan33/openram_testchip/verilog/rtl/user_project_wrapper.v:18: Include file openram_defines.v not found
No top level modules, and no -s option.
make: *** [/home/mkhan33/openram_testchip/mgmt_core_wrapper/verilog/dv/make/sim.makefile:66: io_ports.vvp] Error 1
make: *** [Makefile:62: verify-io_ports] Error 2
m
Looks like you are including it inside the verilog, you should only include it in the includes file.
h
Do not need to include it inside the user_project_wrapper then? The compiler will itself recognize it?
m
Yes, if you add it with the right path.
h
I am getting errors with other files now. Do all the files that exists under 
$(USER_PROJECT_VERILOG)/verilog/rtl
need to be included in the mgmt_core_wrapper includes file?
m
All verilog files used for simulation should be included in the includes file.
h
alright thanks, let me try it out
m
No problem!
h
It works! I think prior to these changes there was 
uprj_netlists.v
for including files needed to do simulation. But now everything moved to mgmt_core_wrapper
m
Yes, that is correct.
h
@User I have to include the 
openram_defines.v
in the user_project_wrapper for the hardening flow, else Yosys errors out not finding the macro defined inside 
openram_defines.v
. But including that defines file causes simulation to not work.
m
@User The includes file is now in the caravel_user_project not litex, as of MPW-5c. I'll check the Yosys issue and come back to you.
@User you need to add it in the config.tcl, you can either add it to the list of blackboxed verilog modules here, or you can add it here if you want it to be synthesized.
h
Yes it works, thanks
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