thanks for any suggestions on integrating the design. I have copied my multiple code files to folder <caravel_user_project/verilog/rtl/>, still reuse the same wrapper 'user_proj_example.v' and 'user_project_wrapper.v'. the hierarchy is : user_project_wrapper.v - user_proj_example.v - counter - function_x.v - block y1.v - block y2.v But there was error during synthesis below, wonder if any specific configuration files need to be changed? synthesis error: Module '\function_x' referenced in module '\counter' in cell 'u_function_x' is not part of the design.

are all your verilog files included in your

user_proj_example/config.tcl

? For example:

set ::env(VERILOG_FILES) "\
        $script_dir/../../verilog/rtl/defines.v\
        $script_dir/../../verilog/rtl/mgmt_protect.v"

thanks, it works. but stuck with standard cell libraries. the '+' and '*' in my code cannot be resolved. any idea? thanks

Sorry, I don't know the verilog - openlane naming restrictions.