Done 🙂 I finally integrated my design in

Caravel

and passed all checks for

MPW-5

. Thanks for all the support and many, many chats! Achievements: • Digital block, hardened in OpenLane • Analog custom block, done in

xschem

and

magic

(and

netgen

and

ngspice)

, integrated in digital-on-top fashion • Logo generated from bitmap Lessons learned: •

magic

is quite usable, despite the first impression 🙂 tutorial is a must • Tools are quick for small toy examples, once the design gets bigger speed suffers; community should invest in making speed better by multithreading • Need a proper solution for the

li1

density issue with the

decap_12

cell • Take

yosys

warnings serious; passing linting and RTL simulation does not mean the design is correct and synthesis will work properly

How did you merge analog and digital?

For the analog you need the .gds/.mag, a .lef and an empty definition in verilog. You can look at my project repo to see how it is done: https://github.com/hpretl/iic-audiodac-v1

Congrats!