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<@U016HU5HK8V>: Okay, found the problem in the last commit; cif/CIFgen.c line 4972 should be `*bls....
# magic
t
@User: Okay, found the problem in the last commit; cif/CIFgen.c line 4972 should be 
*bls.temps
, not 
bls.temps
. I'm not sure why that doesn't just crash immediately, or how it survived the test case I ran before committing the erroneous code. But anyway, it's fixed now (master branch on opencircuitdesign.com ; I have another issue to track down but then I am going to force the github mirror to update rather than leave a bad commit up on the site).
🙌 1
t
Ok, rebuilding now.
👍
Definitely went past the GDS write on both 
spm
and my design. Now lets see if the DRC is any faster than 4h 🙂
(although really it's kind of point less since it returns millions of errors because SRAM)
t
I'm thinking about implementing some kind of method for "ignore this area" when doing DRC checks. It's a little bit tricky in Magic.
t
Yeah that'd be nice. I think I'll move to setting 
MAGIC_DRC_USE_GDS
 to 0 for the time being. I guess that should still provide decent checking since presumably (1) the cells themselves are good and (2) no reason openlane would generate anything in diffusion or poly that could interfere with the abstract view.
One thing I'm worried though is about submission ... because obviously any kind of auto-check on the GDS will fail miserably.
WOW
DRC finished in < 10 min ... vs 4+ hours last time.
t
@tnt: It's what happens when I am not paying attention and put a compute-intensive routine inside a loop that doesn't need to be there. . .
t
😄
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