. Then I unchecked the "diffusion overlap" checkbox (parameter doverlap = 0). What this does: Setting doverlap to 0 normally creates individual transistors and not fingers, spacing them apart by the diffusion spacing difference. So I gave it a negative distance for diffusion spacing, and that causes it to shove the transistors together, giving a double-width via in the middle. Since the diffusion spacing is by default used for the diffusion-to-guard-ring spacing, if you want to enable the guard ring, then you need to set the value for the diffusion-to-tap spacing. There are probably other ways to accomplish this but that seemed the most efficient.
w
Weston Braun
05/20/2021, 9:41 PM
Thanks I will try that!
Weston Braun
05/20/2021, 9:42 PM
laying out my gate driver today. Output stage is 60x 15/0.5 PMOS, 7/0.5 NMOS. Plan is to route metal1 over the gates to connect both sides. And then a wider drain/source connection
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