Hi, I tried to extract the layout with 'extresist on' and found out that some components were missin...
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Hongzhe Jiang
09/09/2021, 3:06 PMHi, I tried to extract the layout with 'extresist on' and found out that some components were missing.
When extracted with 'extresist off':
nfet: 2302
pfet: 7538
polyres: 34
mimcap: 728
total: 10602
When extracted with 'extresist on'
nfet: 844 (missing)
pfet: 7538
polyres: 34
mimcap: 312 (missing)
total: 8428
I am using magic version 8.3.204 which I believe is the latest version. My layout and some extracted files are attached. Any thoughts on this? @User
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Tim Edwards
09/09/2021, 3:24 PMGreat torture test. That'll keep me busy for a while.
Tim Edwards
09/13/2021, 12:43 AMI fixed several issues. The main one for this layout was that none of my testcases had anticipated a label on top a contact and was not handling them correctly. I now get the right number of devices in the output, and the output looks correct by casual inspection (ignoring known limitations of the algorithm, such as that it does not attempt to create substrate or well resistive networks). But I am still getting error messages about missing source/gate/drain when running "extresist", so I am still in the process of tracking those down and determining whether they are a real problem or not. New version is 8.3.206. Thank you for helping to debug the remaining issues!
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Hongzhe Jiang
09/13/2021, 1:22 AMThank you a lot for your time and effort!
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Tim Edwards
09/13/2021, 2:24 PMThe remaining error messages come from the fact that you have "dvss" and "avss" both marked as pins but both sharing the same substrate. I am going to add some code to generate more meaningful output when this happens. There are two solutions: (1) cover the area of "avss" with layer "isosub". this will create an independent substrate region. Note that per my comment above, "extresist" does not extract a substrate network, so these two nets will be completely isolated in the netlist, which is not realistic. (2) (preferred) Since you have room in the layout, drop a deep nwell structure under the entire analog section. This will properly electrically isolate "avss" and "dvss".
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Hongzhe Jiang
09/13/2021, 3:32 PMGot it. Thanks😊
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Tim Edwards
09/13/2021, 3:35 PMActually I just realized that "dvss" is not a port in your design (label only), so the error is that "extresist" is seeing "avss" and "dvss" as separate nets while picking up information from the .sim file where they have been merged. I'm still looking into what is the proper way to handle that, as well as seeing what work is involved in getting an extracted substrate parasitic resistance network.
Tim Edwards
09/13/2021, 4:32 PMThe issue with the "dvss" vs. "avss" nodes in the layout has now been corrected (magic version 8.3.207).
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Tim Edwards
09/15/2021, 8:38 PMMagic "extresist" will now (in version 8.3.209) extract substrate networks through well and substrate from power rails to transistor bulk terminals. The current limitation is that it does not work for implicit substrate and requries that type "pwell" be drawn under all devices over substrate; and use of "isosub" will not be handled correctly . I will be working on those issues next.
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