hello @User and all, I'm checking my design with drc(full) and I see the following strange behavior: on a passgate cell (PASSGATE_v1p1), there's a DRC error (poly contact spacing to P-diffusion < 0.235um (licon.9 + psdm.5a)), while on an inverter configuration (INV_v1p1.mag) with similar layout and sizes, the error doesn't exist. I didn't understand the logic of this, can anyone explain the reason? I attach the cells, any feedback would be appreciated.

The layouts are definitely different spacings. One is 0.12um and one is 0.125um betwen poly and pdiff. I'm not sure about that error reported though.

Indeed, they have 0.005 um difference... which is strange because I generated both using the top menu "Devices 1 > nmos (MOSFET)" and setting the same (or at least I believe so) sizes