@User I currently hunting an LVS issue in an analog layout cell in

magic

using two split VSS. I have the impression I have a short via substrate. Question: Is there a way to split the substrate node in magic, like a marking layer of some sort? (I know from other PDKs that they sometimes have this). Or is it something that I have to simply accept that all NFET bulks are just a shared net?

Yes. Draw the layer

isosub

under all devices that are connected to one of the VSS domains, and it will be extracted as a separate net, without shorting through the substrate.

@User Genius, works 🙂 You might rethink the color and fill of the

isosub

in

magic

, as this layer is virtual invisible. A prime way to seriously confuse the unsuspecting 😄

Noted.