Is there a configuration/command to include the source/drain area+capacitance in post-extracted netlists? Currently, all transistors have the corresponding parameters set to zero i.e.

ad=0.0 pd=0.0 as=0.0 ps=0.0

Two things to know: (1) There was a bug in magic that zeroed out all the areas and perimeters that was fixed in magic version 8.3.242. (2) Magic's extraction method merges together all diffusion areas and perimeters for a single net into one record. Therefore it has a way of lumping all areas and perimeters onto the first transistor S/D connected to the net, and zeroing the rest. It is technically correct for S/D capacitance modeling, although it must introduce some small 2nd-order error for BSIM models. That can be mostly worked around by using the "distributed" area/perimeter option, which divides the areas and perimeters equally among all transistors connected to a single net. That's not exactly correct, but is a much better approximation than lumping everything on the first transistor. Use

ext2spice -d

to enable the distributed area/perimeter option.

Thanks for the pointer. I have updated to the latest version of magic (version 8.3.274) and also updated the pdk but it's still not working. Here is the sample extraction script I'm using:

load "buffer_stage_4_h_3__9.mag"

flatten "buffer_stage_4_h_3__9_flat"

load "buffer_stage_4_h_3__9_flat"

select top cell

extract all

ext2sim labels on

ext2sim

extresist simplify off

extresist

ext2spice lvs

ext2spice format hspice

ext2spice scale off

ext2spice cthresh 0

ext2spice rthresh 0

ext2spice extresist on

ext2spice -d "buffer_stage_4_h_3__9_flat" -o buffer_stage_4_h_3__9.pex.sp

puts "Finished extraction export"

exit

That script would have been helpful to have put in the original post, as it shows you are doing many things in the extraction.

I just confirmed it works without extresist so that must be it

Okay, I'll have to look into that, then.

As an addendum in case this helps further debug, I noticed that with the latest version of magic,

ext2spice extresist on

seems to also impact the correctness of the extraction based on the simulation results. By correctness, I mean a buffer circuit which buffers the input correctly with some delay no longer works as in the attached image. When I inspected the generated netlist, I noticed some floating net comments:

C8 vdd 0 2.11fF
C9 vdd.n0 0 0.00fF $ **FLOATING
C10 vdd.n1 0 0.01fF $ **FLOATING
C11 vdd.n2 0 0.00fF $ **FLOATING
C12 vdd.n3 0 0.00fF $ **FLOATING
C13 vdd.n4 0 0.01fF $ **FLOATING
C14 vdd.n5 0 0.01fF $ **FLOATING
C15 vdd.n6 0 0.05fF $ **FLOATING
C16 vdd.n7 0 0.05fF $ **FLOATING

Late to the thread, but I noticed the same "**FLOATING" addends at some capacitances. I just erased these and the netlist worked quite well (at least on an AC sweep)