Anyone doing LVS on circuits with MOS varactors? I think I'm getting connectivity errors in magic... The varactor PCell should have three terminals (the gate, the "drain and source" and the substrate guard ring), however when I assign labels to these terminals, the third terminal (which I think is supposed to be the substrate terminal) is just short-circuited to the "drain and source" no matter what I do.

The docs show built in N-well to P-substrate diodes - is that accounted for in the PCells layout? I haven't used those cells in magic, so my only familiarity is from what the docs and spice models show

I thing the Nwell-Pwell diode is intrinsic to the model, and that magic for some reason thinks the varactor is a transistor, with their individual source and drain terminals. And, when checking connectivity, magic assigns the third terminal (which is supposed to be substrate) to one of the "drain/source" terminals - which are short-circuited via the Nwell

1. Do you pass DRC? 2. There was bugs related to multi hierarchy deep nwells. Do you use this layer? Did you try updating pdk and magic?

Yes, the circuit is DRC clean. And the PDK and magic are current (if I'm not mistaken) But I'll try updating the pdk and re-run the extract :)

I believe all the spice netlists that I've seen for mos varactors are extracted as 4 terminal mosfet devices using the normal spice format

Mxx D G S B model parameters

As you mentioned, for a mos varactor, the 'source and drain' are the same node, but the extractor splits that into 2 connections to a normal 4 terminal mos device. magic gives a warning when this happens. Happens with the decap cells.

Extracting sky130_fd_sc_hd__decap_4 into sky130_fd_sc_hd__decap_4.ext:
sky130_fd_sc_hd__decap_4: 2 warnings

xschem does package the varactor a 3 terminal device. Magic, from what I saw, does that too, but I think something inside the connectivity checker misplaces one of the terminals during the extraction...

How does xschem export the varactor in the spice netlist? LVS is comparing spice netlists.

It exports as Xn G S B <model name>

Are your model names

sky130_fd_pr__cap_var_lvt

,

sky130_fd_pr__cap_var_hvt

, or

sky130_fd_pr__cap_var

?

sky130_fd_pr__cap_var_lvt I'm using the lvt varactors

@User Any idea why the varactors are extracting as 4 terminal devices?

@User: All tools should be treating the two

cap_var

varactor devices as three-terminal subcircuits, per the model in the file

sky130_fd_pr__cap_var_lvt.model.spice

. Source and drain are always tied together in a varactor, so those collapse to one pin. Since the device is modeled in a subcircuit and not an 'M' device in SPICE, the subcircuit just declares the three independent nodes (the model is actually a SPICE 'C' device with a complicated expression for the capacitance value).

Awesome! Thank you, @User!