@User: I flagged you on a message from Mitch in the #caravel channel. The point in question is that the SRAM in caravel that is only being used like a single-port RAM ended up with the 2nd port address lines unconnected instead of grounded. While I consider this to be bad practice, I don't think it will cause any issues. But I'd like you to weigh in, just in case I'm wrong about that.

Hrm, I'm less worried about din and addr but I'm not sure about clk and csb... That may be an issue.

@Matthew Guthaus Thanks for the response. Just out of curiosity, how do you simulate the effects of Hi-Z input? Would you fix the inputs at VDD/2 and check for current leakage in spice simulation? Or would you set the inputs to 'x' in verilog and see if it caused unexpected output? @Tim Edwards I've heard that given all the variables (temperature, cross-talk, Vth variations, etc.) that it's hard to accurately simulate.

Probably the first. The verilog model is just behavioral and an x will invalidate memory must likely. Trying different values (digital and not) of clk1 and csb1 would be most crucial to see what happens to the control logic and timing