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Hello we are facing this error can anyone provide some help. As we are stuck here. <@U0175T39732>
# openram
h
Hello we are facing this error can anyone provide some help. As we are stuck here. @User
m
I've not seen this before. Can you elaborate what you are doing with your power?
h
i am using eight 1KB sram macros in my design. They are placed successfully in the floorplan. However when i run PDN it throws this error
m
What do you do for the pdn? Is it in your verilog? Are you rotating the memories?
h
@Matthew Guthaus yes i have initiated them in my verilog. And i did not rotate them.
m
What do you have for the power connections in your verilog?
Here is the example of how to do it: https://github.com/AmoghLonkar/openram_testchip/blob/785acbf6f2458dd140fbe4d0d763893f1c356c0f/verilog/rtl/user_project_wrapper.v#L230 The pin names must match inside and outside of the macro. PDN cannot change pin names or connect to different nets outside.
h
yes we have the same name of power pins inside and outside the macro.
m
can you share your repo?
h
Here is my git repo
the sram is initiated in verilog/rtl/BrqRV_EB1/BrqRV_EB1.v
m
where do these get placed?
h
sorry didn't get your question can you please elaborate a little bit
m
How do you do the floorplan?
which is before the PDN
It looks like you don't place the macros
I never had luck with the automatic macro placement
w
The macros were placed like this
m
I see -- that isn't in the repo
Can you share what your setup is?
w
Yes, because it did not go beyond the pdn step
Yes give me a moment
h
@Matthew Guthaus we have added our files in caravel_BrqRV_EB1/openlane/sram/
m
I use the default PDN scripts...
h
ok let us try and will get back to you if we face the same error. Thanks for the help.
w
@Matthew Guthaus It went past that error however now we have a never ending stream of warnings. 
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vccd1 is not explicitly set.
[WARNING PSM-0022] Using voltage 0.000V for VDD network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vccd1.
[WARNING PSM-0030] Vsrc location at (285.520um, 150.880um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (286.200um, 195.640um).
[WARNING PSM-0030] Vsrc location at (425.520um, 150.880um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (426.600um, 195.640um).
[WARNING PSM-0030] Vsrc location at (565.520um, 150.880um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (567.000um, 195.640um).
and it goes on and on
m
This isn't a memory issue. Disabling power grid checking should fix it. You will still see errors in LVS if something is disconnected. set ::env(FP_PDN_CHECK_NODES) 0
h
@Matthew Guthaus As we are using 1KB sram model in our design. So if i reduce the size let say from 256x32 to 64x32 so will it work?
I just have to change the Address Width parameter from 8 to 6. But will the lef file of 1KB will support this config
m
@hamza shabbir we haven't created a memory of that size yet. When the build space is released it will be possible
h
oh so its mean we have the fix memories right now
m
Yes, we have a test chip with various sizes in this run
That is a pretty small memory too. Only 2kbits
h
yes due to area constraints we have to reduce our memory as we had an idea to initiate this small memory 4 times and make it 1KB as we have banking logic in our design. But i think now we have to moved to DFFRAM
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