if anyone is looking for a project to work, creating an efficient schmitt trigger for the HS and/or HD libraries would be useful and likely pretty easy. It could build on the HV version or another implementation elsewhere (Jani & Oza "Low Power Differential CMOS Schmitt Trigger with Adjustable Hysteresis" is for 180nm but has a good discussion on the design, schematics, and a proposed layout so it could be a good starting point). I'm interested in how fast we can get the rise times.

Whilst sometimes useful for dealing with slow external signals, you won't get a faster rise time from a schmitt trigger than you would get from several cascaded stages of ordinary inverters. In the end it is limited by the on-resistance of the fets and the capacitance that it is driving. You could probably optimise it for very fast fall time at the expense of bad rise time though, since in ordinary logic cells, the PMOS devices have to be double or triple the size of the NMOS devices to get symmetrical rise and fall times, and so they add a lot of capacitance that you could reduce if you only care about the falling edge. How fast an edge do you want and what amplitude? You should get well under 100ps without doing anything special at all. What do you want to use it for anyway?

100ps should be fine. I want to generate clean square waves for harmonic frequency multiplication