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When we are debugging the synthesized netlist to find source that is driving unknown values in out g...
# sky130
k
When we are debugging the synthesized netlist to find source that is driving unknown values in out gate-level simulation, we found that the output (
\rst_buf[2]
) of this clock buffer (
sky130_fd_sc_hd__dfrtp_1
) for the reset is unknown, hence everything is not reset properly.
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159294   sky130_fd_sc_hd__dfrtp_1 _45866_ (
159295     .CLK(clk_i),
159296     .D(rst_ni),
159297     .Q(\rst_buf[2] ),
159298     .RESET_B(rst_ni)
Corresponding waveform is shown below
d
Do you have that 
FUNCTIONAL
flag enable, as described here: https://github.com/google/skywater-pdk/issues/310
s
Behavioral model of pdk contains some cells with broken connections so you might facing the same issue. While simulating the Netlist define the macro FUNCTIONAL for using the functional model of pdk cells.
t
Those issues are verilog syntax errors, though, aren't they? My experience has been that if you use one of the broken modules, iverilog won't run at all.
k
@Dan Fritchman @Sajjad Ahmed Thanks for the reply! I also tried with the FUNCTIONAL flag enabled, but there is a `UNIT_DELAY macro that is undefined. Is there a specific value (I'm guessing 1) for this macro? Thanks again!
@Tim Edwards We are using VCS for simulation right now. We could try with iverilog to see if the tool reports a syntax error Thanks!
s
Just define the macro UNIT_DELAY it's working for me without any value.
👍 1
k
I see thanks!
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Error-[SE] Syntax error
  Following verilog source has syntax error :
  "sky130_fd_sc_hd.v", 49280: token is 'module'
  module sky130_fd_sc_hd__lpflow_bleeder_1 (
Relevant source code:
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49279 `celldefine
 49280 module sky130_fd_sc_hd__lpflow_bleeder_1 (
 49281     SHORT
 49282 );
 49283 
 49284     input SHORT;
 49285 
 49286     // Voltage supply signals
 49287     wire    VPWR;
 49288     supply0 VGND;
 49289     supply1 VPB ;
 49290     supply0 VNB ;
 49291 
 49292     sky130_fd_sc_hd__lpflow_bleeder base (
 49293         .SHORT(SHORT)
 49294     );
 49295 
 49296 endmodule
 49297 `endcelldefine
Did this happen to you also? @Sajjad Ahmed
@mehdi @Peijun Hou
m
Where are you using lpflow_bleeder? @Ke-Haur Taur I think that's a level shifter
k
@mehdi You may reference the message at the top of this thread which may provide more context. The problem isn't really about the lpflow_bleeder module. It is about the std cell library file itself. Sajjad provided us the std cell library they are using so the problem went away. The purpose of tagging you in this thread is to give you a heads up on what problem we are working on right now (which you may reference at the first message of this thread).
m
Ok, thanks. Just noting that having level shifters in the design is weird
k
That is not the design file The snippet is part of the sky130_dc_hd.v file.
d
Some time back, i have faced same Error : "
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Syntax error
  Following verilog source has syntax error
I notice there is Typo in sky130_dc_hd.v at Line No: 102454 `endif SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_V This need to changed as `endif //SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_V Due to this tool was reporting error in next module defination
m
@Dinesh A thanks! Do you mind filling a github issue
d
sure
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