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All previous steps are completed successfully but I'm getting error at routing, can anyone please gu...
# sky130
j
All previous steps are completed successfully but I'm getting error at routing, can anyone please guide me about this? Attached are the error and config.tcl screenshots
h
What is your caravel-lite commit?
v
share runs/run1/openroad_issue_reproducible tar file
seems you're running estimate_parasitics -global_routing without running global_route
j
@Vijayan Krishnan Sir kindly check it
file.
v
file format not support what you shared. share as zip or tar file
j
@Vijayan Krishnan Sorry for inconvenience
file.tar.gz
This file is fine or not? @Vijayan Krishnan
v
able to get same issue
j
@Vijayan Krishnan Check now
openroad_issue_reproducible.zip
@Hadir Khan right now I'm just running the openlane flow (not caravel flow)
✅ 1
v
am able to reproduce your issue at my end
working on that.
can you share your config.tcl, so it will be easy to find what are additional settings you added
j
BTW I have attached a screenshot of config.tcl @Vijayan Krishnan But let me send you the complete file as well
I really appreciate your time @Vijayan Krishnan
I'm stuck at routing for like now two days
I'm trying different variables at different steps but it's not working
@Vijayan Krishnan
config.tcl
v
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0 add this in config.tcl and try once
j
Now getting this error at routing @Vijayan Krishnan
v
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# User config
set ::env(DESIGN_NAME) main

# Change if needed
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]

# Fill this
set ::env(CLOCK_PERIOD) "100"
set ::env(CLOCK_PORT) "clk"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 2920 3520"
set ::env(RUN_CVC) 0

set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
	source $filename
}
j
@Vijayan Krishnan If you have time can you take a look at above my repo and guide me about it like which variables should I use to run the flow
v
try this config.tcl once and let me know
which openlane version are you using?
j
I just installed it a week ago tbh I don't know which version is this
but I think this must be the latest bcz I installed just a week ago
v
in the repo link which is your top design
j
top_level.v
v
i'm updating my openlane repo now. Update you once i check it
j
In instruction_memory.v I read machine code from .mem file so if you will not add that file it will give error
let me send you instruction_memory.v file with some hard code machine codes
@Vijayan Krishnan you can use this
Instruction_Memory.v
v
👍
j
getting same estimating parasitic error with your config.tcl as well
v
11. Executing Verilog-2005 frontend: /openlane/designs/risc32_scp/src/Controller.v /openlane/designs/risc32_scp/src/Controller.sv2v.v12 ERROR: syntax error, unexpected TOK_CHECKER, expecting TOK_ID or '#' [ERROR]: during executing: "yosys -c /openlane/scripts/yosys/synth.tcl -l /openlane/designs/risc32_scp/runs/1strun/logs/synthesis/1-synthesis.log |& tee >&@stdout"
facing issue at synthesis itself
j
let me send you updated file
use this file, although it does not have any syntax error earlier as well but I don't know why it gave this syntax error
Controller.v
but with this file you will not get this syntax error @Vijayan Krishnan
v
I'm not able to get same error with the repo.
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config: /openlane/scripts/openroad/pdn_cfg.tcl
[ERROR PDN-0085] Pitch 3.6799999999999997 specified for layer met4 is less than 2 x (width + spacing) (width=3.0, spacing=1.84).
Error: pdn_cfg.tcl, 39 PDN-0085
j
so noe what is this error?
and can you share your config.tcl
v
# Change if needed set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v] # Fill this set ::env(CLOCK_PERIOD) "10.0" set ::env(CLOCK_PORT) "clk" set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl if { [file exists $filename] == 1} { source $filename } set ::env(SYNTH_READ_BLACKBOX_LIB) 1 set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS" #set ::env(FP_SIZING) absolute #set ::env(DIE_AREA) "0 0 2920 3520" set ::env(RUN_CVC) 0 set ::env(FP_PDN_CORE_RING) 1 set ::env(FP_PDN_CORE_RING_VWIDTH) 3 set ::env(FP_PDN_CORE_RING_HWIDTH) $::env(FP_PDN_CORE_RING_VWIDTH) set ::env(FP_PDN_CORE_RING_VOFFSET) 14 set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET) set ::env(FP_PDN_CORE_RING_VSPACING) 1.7 set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING) set ::env(FP_PDN_VWIDTH) 3 set ::env(FP_PDN_HWIDTH) 3 set ::env(FP_PDN_VOFFSET) 5 set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET) set ::env(FP_PDN_VPITCH) 180 set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH) set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)] set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)] set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}] set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}] set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS" set ::env(FP_PDN_CHECK_NODES) 0
seems i'm running wrong repo of verilog source code. zero instance found from the top file you gave. Please provide right src zip file
j
source repo is upto date
there might be some other issues
v
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30. Printing statistics.

=== risc32_scp ===

   Number of wires:                  2
   Number of wire bits:              2
   Number of public wires:           2
   Number of public wire bits:       2
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0
no cells found from your verilog code. I just changed top module name main to risc32_scp
j
so what does this mean?
like my verilog files are wrong?
v
can you share your runs/logs/synthesis/1_synthesis.log
j
1-synthesis.log
1-synthesis.log
v
same in your end aslo
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Number of wires:                  2
   Number of wire bits:              2
   Number of public wires:           2
   Number of public wire bits:       2
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0
j
it is tested design through vivado
i have syhthesised it using vivado and it's fine
what do you think issue might be?
bcz it's a tested design
ok so what can you infer through errors which you are getting during flow?
all files are completely in verilog
v
using the repo source file, zero instance used, so tool not doing any placement
first time am seeing this error. Raise github issue, some one will guide you
j
BTW you are purely backend engineer?
v
yes
j
you have also happened to work on cadence tools?
can you give me your email id bcz I have couple of other desighns as well like 5 stage pipeline and I'm also implementing some peripherals as well so will you be willing to help me with them if I need any?
v
you can DM here itself or raise github, other experts will help you
j
ok can you share some backend resources for beginners
like there is almost nothing available when it comes to backend
v
j
ok I really appreciate your time,
thank you so much
I try to find out like what is the issue in verilog files
v
@Junaid amjad I checked with Frontend team. The verilog looks ok. But during yosys synthesis top level unconnected signals removed by OPT_CLEAN.
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15.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..
Removed 1010 unused cells and 1736 unused wires.
<suppressed ~1104 debug messages>
Need to find option to skip this
j
@Vijayan Krishnan So what do I need to do now?
like you are saying that my top level connections are wrong or what?
v
@Junaid amjad can you tag yourself in the above github issue. Answer the experts question, so it will be resolved else it will be closed
d
@Junaid amjad
j
@donn yes you are right, design does not has any output because it's very basic level single cycle processor that's just executing instructions and as memories are also part of core so even data is also not an output. I'm working on implementation of some peripherals like, UART, SPI, RAM etc. I just try this design to understand the flow of Openlane. so if I just add a dummy output variable, will my design be able to complete the openlane flow?
d
yes.
To be precise, the output variable needs to actually amtter
If it's an empty wire, it'll still be optimized out
j
like an empty wire will work or not?
d
It will not work.
j
So I have to assign that output something that always going to get some value
d
you have to assign it to something in your circuit. like the read data from memory
j
Got you
thanks @donn
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