@User @User Fellas, I need help in chip integration. I am not familiar with digital flow (openlane). I have analog designs and I would be happy to route IOs manually but I don't know how to configure the IO cells for analog. Can I simply route top metal to the PAD (no passivation area) and bypass all the IO cell configuration? Normally, for analog designs I create a pad ring cell and then instantiate my top level cell in it and connect the Top cell pins/ports to the IOs. Can I do something similar? Need recommendations................

We are doing one for tapeout. PNR is pending. But you can refer to below link https://github.com/rsnkhatri3/vsdPLLSoC

@Affan Abbasi I also am just doing an "Analogue on Top" flow and routing to pins. You need to use the

user_project_wrapper.gds

and route your signals to the analog_io pads. There's some confusion around these at the moment and the offset (see Sylvain's comment). If you haven't seen it already check out: https://github.com/yrrapt/amsat_txrx_ic-caravel/blob/master/analogue_integration.md Please suggest any improvements or things you find out