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Hello, I am testing LVS over the user_analog_project_wrapper in a minimal design with just 1 opamp (...
# analog-design
f
Hello, I am testing LVS over the user_analog_project_wrapper in a minimal design with just 1 opamp (I have excluded other cells in order to isolate the error). Initially netgen says (for both nfet and pfet):
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Warning: Equate pins:  cell sky130_fd_pr__nfet_01v8 has no definition, treated as a black box.
and at the end of the comparison file it states:
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Device classes user_analog_project_wrapper.spice and user_analog_project_wrapper_layout.spice are equivalent.
Verify:  cell user_analog_project_wrapper_layout.spice has no elements and/or nodes.  Not checked.
Does someone experienced this behaviour? I understand that netgen is not reading the transistors in the extracted file, then no comparison is made.
user_analog_project_wrapper.spicecomp.outuser_analog_project_wrapper_layout.spice
y
Are you using the sky130 netgen configuration script when you run netgen?
Also, I don't think your vdd or iref pins are correctly connected to the user_analog_project_wrapper pins
f
yes, I am using the script provided by open_pdks
that's correct, the iref pin have been left unconnected in this version in both sch and layout, but the vdd should be ok, I'll check that, thank you
I have solved this issue, have been extracting the top level layout using
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extract all
ext2spice lvs
ext2spice -o cell_ext.spice
this created a subcircuit instance of the top layout. The netlist matches uniquely after commenting out the lines containing the ports and the subcirtuit declaration (i.e., including only the instances of our cells)
y
Good to hear you solved it
f
Thank you, @yrrapt ! 🙌 Now dealing with the GDS file
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