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Is there a formula anywhere in the PDK to calculate AD, AS, PD, PS parameters for MOSFETs? I have se...
# analog-design
m
Is there a formula anywhere in the PDK to calculate AD, AS, PD, PS parameters for MOSFETs? I have seen someone using 0.29um to multiply it by each finger's gate width. I cannot find any reference to it in the PDK. More importantly, are there any parametric cells for schematic or layout instances for any tool flow?
t
If you want an estimate of the values, look at the xschem libraries for sky130, which are using the recommended method.
m
Where would you find the formulas for that recommended method?
t
You can ask in the #xschem channel. I'm not sure if that came from documentation or just from assumptions about the minimum amount of diffusion needed for source and drain.
m
I found them. The same 0.29(um?) number popping up in them as well. I suspect it assumes the minimum width for source and diffusion widths. For the layouts, are there any parametric cells created? I know very little of Klayout and no Magic.
s
Given a total width '`W`' and number of fingers '`nf`' the formulas are for (drain):
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ad=int((nf+1)/2) * W/nf * 0.29 
pd=2*int((nf+1)/2) * (W/nf + 0.29)
For source as and ps same formulas are used. The 0.29 value is presumably the minimum gate to contact + contact + diffusion endcap over contact.
m
They make sense. Still need to dig in to design rules to make sure.
s
the tricky int((nf+1)/2) is used to handle transistors with even/odd number of fingers.
I was mistaken, since in transistors with even number of fingers the number of drain/source areas are different these are the formulas used in the mos symbols.
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ad=int((nf+1)/2) * W/nf * 0.29 
pd=2*int((nf+1)/2) * (W/nf + 0.29)
as=int((nf+2)/2) * W/nf * 0.29 
ps=2*int((nf+2)/2) * (W/nf + 0.29)
m
Sorry I was in a hurry when I answered the question. My answer was really about multiple devices, not multiple fingers.
For multiple fingers, if nf is even: AS= W x l AD= (nf-1) x (W/nf) x l
if nf is odd, then AD=AS=W* l
Of course, it is a gross simplification. First of all we need to know two design rules: minimum distance from contact to poly gate and minimum coverage of contact by diffusion. The figure below shows the idea in lambda rules:
Because design rules are just numbers without any plots, its difficult to get an idea about these spacing rules. I think the minimum contact size is 0.17um and spacing is 0.19um. Correct me if I am wrong.
Thus, the use of multiple fingers may not bring much advantage in reducing the junction parasitics in drain. Cadence parametric cells quite often has the option of
swapping Source and Drain diffusions if for example you are more worried about reducing source capacitance, e.g. in common-gate amplifier.
For layout design rules, it would be very beneficial Skywater were to release drawings for the rules with various spacings.
t
There are drawings posted with the design rules, although they are poorly done and sometimes hard to read. It's all that SkyWater has, though.
m
Then they need to improve it if they want to be in the foundry business.
I checked a gds for a gate from the library. I think the minimum diffusion width is 0.26um if there are poly at both sides and 0.255um if there is poly only on both sides for PMOS. I think the discrepancy should be a result of spacing rule between licon and poly. For NMOS, the rules seem to be 0.28um and 0.285um for NMOS.
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