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we are running post layout simulation for a simple inverter included in the following files: but we ...
# analog-design
m
we are running post layout simulation for a simple inverter included in the following files: but we get zero output as shown below Any help @User @User Thanks in advance
subcktinv_pex_2
l
Your subcircuit pins are
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.subckt TOP INPUT OUTPUT GND VDD
while your testbench instance is
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Xs INPUT OUTPUT VDD 0 TOP
This happens because when you extracted the circuit from the layout, the GND pin was labeled first. Spice is a really bad language for pin order...
m
OH i am sorry okay thanks
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