hello all, I'm wondering which capacitive load values are people here using in their testbenches to carry the signals off-chip through the analog pads, any idea? just to consider for the output buffer design

I am using 6pf, but I am JUST assuming pad's capacitance is ~1pf and my inputs (of the other device) is 5pf

thanks! I found this reference " The capacitive load when transferring a signal off-chip to the surrounding world is about 10-50 pF, which indicates that we need a transistor 1000 times stronger to drive the off-chip load. Therefore, output buffers are necessary when the circuit is sending information out from the chip." in https://www.isy.liu.se/edu/kurs/TSEK06/kursmaterial/TSEK06_ProjectGuide_1.5.pdf I remember I was using around 10pF some time ago, I wanted to confirm with other

The data might be old. For example HyperRAM input capacitance is 3pf and (I would assime that) the sky130 I/O pads capacitance cant be higher than 1pf. Depending on what task you are targeting, the test capacitance might change. Is it a highpower mosfer? Use higher values. Is it another chip that has datasheet? Use stat from the datasheet + your I/O estiamted capacitance. Is it a long wire? Target high capacitance, low rise/fall times