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Hi! I am implementing an analog circuit and I'm have the following errors in the precheck. Does some...
# analog-design
w
Hi! I am implementing an analog circuit and I'm have the following errors in the precheck. Does someone know what this means?
a
You need to have valid netlist in netgen/user_project_analog.spice
It compares them with your GDS
w
Yes. But I'm having problems with extraction. I have a connection on the VSSA1 pin, but in the extraction it shows vccd2.
a
is your lvs clean?
I had issue where vss of a lot of components where shorted. This was due to magic/olen pdks version. This only happened when the cells where located on dnwell. I flattened the design and it fixed the issue
w
I was implementing two blocks and connected them as cells in the user_analog_project_wrapper_empty. The lvs is clean when I run each block separately. But when I insert the blocks to the top, the VSSA1 pin is extracted as VCCD2 and fails the pre-check. I'm using magic layout. I received the following message in the precheck: " PORTS CHECK FAILED: user_analog_project_wrapper ports do not match the golden wrapper ports. Mismatching ports are : ['vssa1']".
t
Can you post a link to your layout?
w
This is the repository with the envelope detector and OTA blocks: https://github.com/wislamilena/receiver.git
I made the submission yesterday just the envelope detector ( this is the repository: https://github.com/wislamilena/my-chip.git). The top with just that block passed the precheck. When I put the other block (OTA), the problems appeared and I couldn't solve them before the submission deadline.
t
In your 
otaV5
circuit, you have both 
Vp
and 
Vn
conntected to the same output, 
vccd2
. The two ports to which they are connected belong to the same pad. Since 
Vn
has a substrate connection, then 
vccd2
is shorted to 
vssa1
through the substrate.
w
Ah, I understand! Thank you. Will there be a deadline to update the repository for tapeout?
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