Mm, yosys is converting some of my

posedge

FFs to negative edge ones (

sky130_fd_sc_hd__dfbbn_2

) prefixing the clock path with an inverter ... I'm not a big fan of that.

have you tried below?

OpenROAD-flow/flow/util/markDontUse.py

Yeah I could mark those as don't use, but it's not that I object to negedge FF, I just don't like it inverting the clock to use them 😛 But if I have a

negedge

in my verilog, I'm fine, it can use it.

I see your point… doc mentions use of inverters is acceptable, may need enhancement. There is also an optional “selection” argument to dfflibmap, you may be able to work around this if you can identify the problematic banks beforehand

Where is the don't use list in openpdk ?

Feel free to revise/experiment with the

no_synth.cells

file (incrementally allowing smaller and different cells, etc.). The file was created with the older set of tools. Cells, whose pins were difficult to access back then, were added to the list, so that's why many of the cells are of size 4. The file is at

$PDK_ROOT/sky130A/libs.tech/openlane/sky130_fd_sc_XX/no_synth.cells

.

Ah yeah

no_synth

Tx ! I was grepping for

dont

and

use

and not finding it 😛