@User: "Hardening" generally means taking a design and running it through place and route and generating all the various files (LEF, GDS, SPICE, etc.) needed for it to be treated as a "hard macro" block in a larger design (anywhere in the hierarchy up to the chip top level).

Ah ok cool.so this is what you were suggesting for my aggregation plan. Harden all the designs separately then link them at the top level?