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Let's say I have a picorv32 cpu already hardened. It has a wishbone bus. Now I write a peripheral an...
# openlane
m
Let's say I have a picorv32 cpu already hardened. It has a wishbone bus. Now I write a peripheral and harden that. How do I put those blocks together and get them wired up?
Or I have some extra memory from openram, how does that wiring happen?
t
you use them as macro in your top level design (basically black boxes).
AFAIU This is currently not fully implemented in the flow.
(although really for your picorv + peripheral, you would just synthesize both at the same time ...)
m
It's for this aggregation idea I have. I want to put lots of smaller designs together. So they will all be macros with some common connections
I suppose it must be planned tho because otherwise how would you use a tool like openram? Or wire it up manually in magic...
t
yeah, it's planned and you can see the beginning of the implementation of it in the flow, but it was not fully functionnal. There was an example with a macro in 
rc1
but it's been removed because it wasn't running in the current flow.
m
Thanks
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