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This small design has 2 clock inputs that are muxed depending on external signal: <https://github.co...
# openlane
m
This small design has 2 clock inputs that are muxed depending on external signal: https://github.com/GuillemCabo/ASIC_watch/blob/2abd377cc5383e411fc9bbb33b881d98d1eaee78/hdl/watch_hhmm.v
a
What's the internal clk net called tho?
m
clk_crystal_i
a
Is that what shows up being connected to the CLK pins of cells in the gate-level netlist?
m
It's like @tnt says: That design uses a lot of different clocks, all going to relatively few cells.
the clock is divided down to get lots of different slow clocks
t
Basically this "clock" design generate a 1 second clock, a 1 minute clock, a 1hour clock etc ... all through clock dividers so you have a bunch of different nets clocking FFs.
a
@Matt Venn: You should be able to set multiple values for 
CLOCK_NET
. (e.g., 
"clk_crystal_i clk2s_int clk1m_int ..."
) I would check the actual gate-level netlist to make sure that these nets didn't get renamed by yosys though.
m
I've been having this same issue, so I'm glad this was brought up. Probably a noob question, but where in the output directories can I find the gate-level netlist?
Is it runs/<design>/results/<design>.synthesis.v?
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