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Hi everyone! I asked this already in <#C016G7Z8GDR|general> and was redirected here, so here is my q...
# openlane
f
Hi everyone! I asked this already in #general and was redirected here, so here is my question again: I have a problem with OpenLane and building a VERY small example. It fails with an error message during "Generating PDN" process. The log is attached. The two core error messages are "Error: cannot open '/.openroad'." (which seems to be normal) and "Unexpected error: can't read "stripe_locs(met4,GROUND)": no such element in array". I tried the process using these two guides:

https://www.youtube.com/watch?v=d0hPdkYg5QI▾

https://inst.eecs.berkeley.edu/~cs250/fa20/labs/lab1/ Both fail with the same error. However, the "make test" worked flawlessly. What I basically did: $ flow.tcl -design my_design -init_design_config Edit designs/my_design/src/my_design.v (see attached file) $ flow.tcl -design my_design Any suggestions?
pdn.logmy_design.v
Syntax highlighting in Slack helps. I had a typo, its "input" not "intput"... Strange message for a syntax error...
Now PDN passes and he failes with Error: Util exceeds 100%. Please double-check your die/row size
To solve my own problem: The die size was not large enough (basically what the messaged said), but figuring out how to increase it, was a pain. In the end (please correct me if there are better solutions) I added these two lines to my config.tcl: set ::env(FP_SIZING) "absolute" set ::env(DIE_AREA) "0 0 30 50" Interestingly the die area has to be given in mm here instead of µm what the documentation says. Then I came accross a second error, complaining that the clk net was not found. Although it existed, it was not considered a clock net, because it was driving only a single target, which is correct for my very small design. So I added a second input and output pin, connected them though a flip-flop in the verlog code and everything works now 🙂
a
have you seen this? you could have tried changing the PDN pitch/offset too https://github.com/efabless/openlane/wiki
f
There should be a wiki with all the abbreviations used throughout this project... I am completely new to chip design and I noticed that OpenLane is not the right place to start with.
So, yes I saw that page but it does not help me 😋
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