I am on

mpw-two-c

on

caravel_user_project

and I am on

v0.15

on

openlane

I am running

make user_project_wrapper

with my own design instantiated in

user_proj_example

I noticed that in

1-yosys

I will get about ~200 warnings that say every output wire in

user_project_wrapper

is used but has no driver (screenshot below) even though these wires are driven by my logic / driven to a constant value. Any suggestions on what is going on here?

I think this is normal, I also get them

Thanks matt! Good to know