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Hi, I've been trying to generate pdn for my design using gen_pdn command, but it has been stuck here...
# openlane
a
Hi, I've been trying to generate pdn for my design using gen_pdn command, but it has been stuck here since the past 2.5 hours. Has anyone else faced a similar issue?
One important thing here is that, I've used a netlist generated through Genus as we have our rtl in systemverilog. I am using openlane for steps floorplan onwards.
m
@Aireen Amir Jalal Yes, the current solution is to disable this check by setting 
FP_PDN_CHECK_NODES
to 0
a
Thanks @Manar Abdelatty this setting worked out! I am now facing a similar issue at detailed_placement_or step. It's been stuck here for a while now. Any settings for this case too?
Nevermind it completed! Thanks
Hi, @Manar Abdelatty, I am currently on the cts stage and its been almost 10 hours but the flow is stuck at this stage. Am I missing some important parameter setting here?
m
@Aireen Amir Jalal I amn't completely sure but it could be stuck at the resizer stage due the high 
wns
, you can increase the clock period to address the negative slack.
a
@Manar Abdelatty, I tried setting this variable 
CTS_REPORT_TIMING 0
and it went past this stage.
Sure i'll try it with increased clock period as well. Thanks
@Manar Abdelatty, Any leads on how to solve this global route issue?
m
@Aireen Amir Jalal I would try changing the 
PL_TARGET_DENSITY
or 
GLB_RT_ADJUSTMENT
a
What values would you suggest? I've tried ranging 
GLB_RT_ADJUSTMENT
from 0.3-0.55 and 
PL_TARGET_DENSITY
to 0.7 but the error still persists.
@Manar Abdelatty, can you please point out the possible reason for this log error at place_io step.
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