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My design has finished everything with no errors (I think) but then during LVS, I get a mismatch in ...
# openlane
m
My design has finished everything with no errors (I think) but then during LVS, I get a mismatch in number of nets:
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Circuit sky130_fd_sc_hd__or4b_2 contains no devices.                                                                                                                                         
Contents of circuit 1:  Circuit: 'user_project_wrapper'                                                                                                                                      
Circuit user_project_wrapper contains 628418 device instances.   
...
Circuit contains 3964 nets, and 307 disconnected pins.                                                                                                                                       
Contents of circuit 2:  Circuit: 'user_project_wrapper'                                                                                                                                      
Circuit user_project_wrapper contains 628418 device instances.  
...
Circuit contains 3801 nets, and 371 disconnected pins.
If the router thought it finished, where would these come from? Is this maybe related to antenna diodes?
Ah, it could be due to disconnected supply rails if the rows are too short?
They all seem to have vertical straps over the rows at some point
I think this might be related to connected pins. When i was floorplanning a block, I made it so that there was a left and right version of several pins for physical access. Internal to the macro, they were connected. However, it seems that the router only connected one or the other!
@Amogh Lonkar I am removing the left/right pins, can you verify this doesn't change functionality?
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a
Functionality is the same
t
Have you checked detailed report from LVS ?
m
I will but it's taking a LONG time
@Tayyeb Mahmood I've narrowed it down that somehow it disconnects din and dout of my memories after synthesis. In the .synthesis.v it is fine, but in .synthesis_optimized.v they are disconnected
r
@Matthew Guthaus were you able to solve this problem?
m
@Rameen Anwar not yet
I made a simpler test case where I have two memories, a single port and dual port, both hooked up directly to the LA. The din/dout of the single port get disconnected just like my other test case. There's no logic here for Yosys to infer that it is redundant
Figured it out. The pins on the LEF didn't match the verilog....
r
we are getting Mismatch for decap and filler cells only, during LVS check
m
@Rameen Anwar I was using some other experimental memories
The dual port should be working fine in the flow
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