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Does anybody know what the implications of the various `DIODE_INSERTION_STRATEGY`s are? Basically, w...
# openlane
p
Does anybody know what the implications of the various `DIODE_INSERTION_STRATEGY`s are? Basically, we're going to paste a macro I generate into a larger design, and manually hook it up to something else (i.e. literally just draw in new rects on the metal layers). Because of this I'd prefer that there are diodes on all the output pins of my macro, at the very least. Will the default diode insertion strategy (3 "use FastRoute Antenna Avoidance flow") probably suffice? Also, does anybody know if diode strategy 1 ("spray diodes") will put diodes on just the pins of my macro, or literally just like everywhere (just filling my design with a bajillion diodes to avoid any antenna check violations)? Relatedly, how concerned should I be about this output in my 
manufacturability_report.rpt
?
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Antenna Summary:
Source: /openLANE_flow/designs/snproc/runs/run7_rev2_mem512/reports/routing//41-antenna.rpt
Number of pins violated: 960
Number of nets violated: 651
m
I had a problem with the default strategy so I switched to strategy 1: https://skywater-pdk.slack.com/archives/C016H8WJMBR/p1623966399484800
p
@Matthew Guthaus Okay, interesting, thanks. Weirdly, synthesis with strategy 1 actually totally failed for me.
m
How did it fail?
p
I think I got "too much congestion", but I can double-check.
Do you know how inefficient strategy 1 is? Is it literally just inserting like a bajillion diodes everywhere, to discharge every single net? If so, that sounds really inefficient.
m
I have no idea, to be honest
I thought it would distribute a bunch of diodes and then insert them as needed
p
Okay, interesting, thanks. I'll ask in #shuttle.
Okay, wait, it actually says: 
[WARNING DPL-0005] Overlap check failed (14269)
By the way, your question on muxing clocks yesterday was very helpful, I actually had exactly the same question, and came to Slack to see that you had asked about it just a few hours earlier.
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