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they aren't used in your design so they got optimised out?
# openlane
m
they aren't used in your design so they got optimised out?
k
Hi, in fact I use them
it is really strange, because other inputs work fine
and the functional simulation works too
there is something bad in the Yosys because on the generated netlist you can see those ports but not connected to anything
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cic  cicmodule( .clk(clk),
                  .rst(rst),
                  .we(mclk),
				  .data_in(pdm_data_i),
                  .data_out(cic_out)
                  );
m
I would guess it is optimising part of your design out because it detects it's never used
read the synth log to get more clues
k
there is nothing reported however I am revising the code of the cic module written by students ...
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module cic #(parameter N = 16)(
  input wire clk,
  input wire rst,
  input wire we,
  input wire data_in,
  output reg [N-1:0] data_out
);

	always@(posedge clk) begin
		if(rst)
    	    data_out <= 0;
    	else if(we)
       		data_out <= data_out + {{15{1'b0}} , data_in };
	end 
   
endmodule
just simple ff in cic module however still got unconnected port
the signals mclk = we and pdm_data_i = data_in are evidently used
got it !!!
a few modules after the cic module there was an assignment which cut the datapath, I have connect it and now it works. Truly the optimization problem. Thanks for giving a hint.
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