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Hi, is there a way to use `always` blocks, `!` or `~` inside the user_project_wrapper? I get the fol...
# openlane
r
Hi, is there a way to use 
always
blocks, 
!
or 
~
inside the user_project_wrapper? I get the following erros when I do make user_project_wrapper . I get the following errors: • With 
always
: 
unexpected REG Error: or_sta.tcl, 31 STA-0164
• With 
!
I get: 
module $logic_not not found
• With 
~
I get: 
module $not not found
Any idea or any suggestion? Thanks.
v
always do attach complete log file for debugging
m
you can't do any thing that requires synthesis in the top level user_project_wrapper
only wiring
r
Ok, thanks. But I have seen projects from mpw2 that they do it. Maybe it's something new?
m
copy the way the user_proj_example is done: a smaller module that is hardened on its own, and then just wired in at the top level
no, it's never been done
well I'm not saying people haven't tried - just that the config has never supported it
r
I have seen it in the operan_testchip. Ok, I will do something like the user_proj_example
Thanks for answering
m
np
can you link the project you think does it?
I'm curious
r
go to line 119
m
ok yes,
and they have also changed the config
to make top level synthesis work
I don't know the ramifications of that, perhaps @User could shed some light on that
r
ahhhhhhhhhhh, I see. Is that allowed and recommendable? Or it is better to harden some macros even that they are small to do that logic and then place all the macros in the wrapper?
m
still, I would avoid doing it myself because anything you do differently gives more places for weird problems that other people will then struggle to help you with
personally I wouldn't recommend it
r
ok, thanks
m
This was on mpw2. I don't believe there should be any issue with it but Matt is right that it was different.
@User how can you connect the power pins of the SRAMs if they are inside a macro? Placing all of the logic in a hardened block was going to affect the timing of the wrapper logic too much so we avoided it.
m
yeah that was a problem for a lot of people not being able to do synthesis at the top level. I don't understand the reason for it
r
In fact, commenting 
set ::env(SYNTH_TOP_LEVEL) 1
makes my project to don't find the openRAM module macro
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