https://open-source-silicon.dev
Join Slack
<@U02GFJ31X8A> Check `&lt;design&gt;/runs/&lt;tag&gt;/results/lvs/&lt;design&gt;.*log`. Can you see ...
# openlane
m
@User Check 
<design>/runs/<tag>/results/lvs/<design>.*log
. Can you see which pin is giving the error?
k
Hi, I have the same problem, the issue is with vcc and vss
Copy code
Subcircuit summary:
Circuit 1: user_project_wrapper            |Circuit 2: user_project_wrapper
-------------------------------------------|-------------------------------------------
user_proj_example (1)                      |user_proj_example (1)
Number of devices: 1                       |Number of devices: 1
Number of nets: 608 **Mismatch**           |Number of nets: 609 **Mismatch**
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: user_project_wrapper            |Circuit 2: user_project_wrapper

---------------------------------------------------------------------------------------
Net: vssd1                                 |Net: vssd1
  user_proj_example/vssd1 = 1              |  user_proj_example/vssd1 = 1
  user_proj_example/vccd1 = 1              |
                                           |
(no matching net)                          |Net: vccd1
                                           |  user_proj_example/vccd1 = 1
---------------------------------------------------------------------------------------
Netlists do not match.
Netlists do not match.
@User @User As far as I was able to debug it it is related to the relative position of the macro in the user_project_wrapper. I suppose it should be aligned somehow with the metal straps of the wrapper
in my case it also produces a lot ot DRC
Copy code
Magic DRC Summary:
Source: /project/openlane/user_project_wrapper/runs/user_project_wrapper/reports/magic/36-magic.drc
Violation Message "Metal4 > 3um spacing to unrelated m4 < 0.4um (met4.5b) "found 32 Times.
Violation Message "This layer can't abut or partially overlap between subcells "found 51 Times.
Violation Message "Metal1 spacing < 0.14um (met1.2) "found 1734 Times.
Violation Message "Metal2 spacing < 0.14um (met2.2) "found 97 Times.
Violation Message "via4 width < 1.18um (via4.1 + 2 * via4.4) "found 1 Times.
Violation Message "Metal3 spacing < 0.3um (met3.2) "found 103 Times.
Violation Message "Metal4 spacing < 0.3um (met4.2) "found 27 Times.
Violation Message "poly overlap of poly contact < 0.08um in one direction (licon.8a) "found 146 Times.
Violation Message "Metal5 spacing < 1.6um (met5.2) "found 432 Times.
Violation Message "Via1 width < 0.26um (via.1a + 2 * via.4a) "found 2 Times.
Violation Message "via4 spacing < 0.42um (via4.2 - 2 * via4.4) "found 6 Times.
Total Magic DRC violations is 2631
m
@User looks like vssd1 is shorted to vccd1. I'd take a look at the DRC errors before worrying about LVS, though. Macro alignment would be a good place to start, I suppose.
k
@User I ran the flow for the default macro position and it gives me this
Copy code
Subcircuit pins:
Circuit 1: user_project_wrapper            |Circuit 2: user_project_wrapper
-------------------------------------------|-------------------------------------------
vssd2                                      |vccd1 **Mismatch**
vssd1                                      |vssd1
wb_clk_i                                   |wb_clk_i
wb_rst_i                                   |wb_rst_i
wbs_ack_o                                  |wbs_ack_o
m
LVS and DRC are clean for 
user_proj_example
, correct? I suggest you check that the vssd1 and vccd1 pins on 
user_proj_example
fit the grid for 
user_project_wrapper
.
k
yes
that what I was thinking
there are 4 straps for positive potential and 4 for grounds
seems that my vcc1 is shorted to the vss2 what is a bit werid, assuming the same macro size and the same position
r
How can I know what vccd or vssd I have to use? It depends on the site of my macros? Where can I find the information?
m
k
@User if You use digital use vssd1 and vccd1
r
I'm using digital, but it says mismatch with vccd1 and it works with vssa1
k
look, I have solved the problem, just use the default position of the macro and if You want to change it move it vertically by a factor of 180 (pitch) that worked for me
r
but i have a lot of macros
well, not a lot 6
so, I need to move macros in both axis, X and Y
k
move freely along X axis
and Y try to arrange by a factor of N*180
r
and N is any number that I want? 1690 that is the default place of the default macro is not a multiplier of 180
k
You are right, I wasn't precise. What worked for me was to move the macro from the default position 1690 by a factor of 180
r
ok, thank you. So 1690-N*180 would be a starting point for me
k
gie it a try
r
If I put one of the macros that im trying to put (and the other ones commented in the macro.cfg and also in the user_project_wrapper.v) in the same position as the example macro: 
#mprj 1175 1690 N
chip_controller 1175 1690 N
with: ``ifdef USE_POWER_PINS` 
.vccd1(vccd1),  // User area 1 1.8V power
.vssd1(vssd1),  // User area 1 digital ground
``endif` It gives me: 
Subcircuit pins:
Circuit 1: user_project_wrapper            |Circuit 2: user_project_wrapper
-------------------------------------------|-------------------------------------------
vssd2                                      |vccd1 **Mismatch**
vssd1                                      |vssd1
wb_clk_i                                   |wb_clk_i
wb_rst_i                                   |wb_rst_i
However with: ``ifdef USE_POWER_PINS` 
.vccd1(vssa1),  // User area 1 1.8V power
.vssd1(vssd1),  // User area 1 digital ground
``endif` It works, and I'm not using analog, only digital things. I'm scared and I suppose that something is wrong
And this last time it also doens't work with the vssa1 in the default position. But it worked in chip_controller 2300 700 N with vssa1 and not vccd1
k
I understand You,
vssa1 is analog ground
I will pass You my flow, I hope will work for You
the other thing is be sure that booth macros gds/user_project_example.gds and lef/user_project_example.lef get updated each time You make it
forget the last ne, this one is the valid
r
I don't understand this: "the other thing is be sure that booth macros gds/user_project_example.gds and lef/user_project_example.lef get updated each time You make it". I have the gds and lef generated for all my macros
@User, @User What is the science behind the macro placement in the user_project_wrapper in order to know what coordinates are the ones that are right to put a macro in the macro.cfg that will work with vccd1 and don't get LVS errors?
@User I have seen your repo for MPW3 that you use different macros. In your macro.cfg I have seen that you use decimals. How do you calculate where to place each macro?
I fixed the vssa that should be a vccd making my macro bigger
m
I measured the distance and worked out the routing grid size
Open in Slack
PreviousNext
Powered by

What is Linen?

Linen is a search-engine friendly community platform. We offer integrations with existing Slack/Discord communities and make those conversations Google-searchable.

Powered by